With the increasing clock speeds and decreasing feature sizes of VLSI (very large scale integrated) chips, analysis of electrical properties of wiring that connects various devices on the VLSI chip has become extremely important. Several tasks such as noise analysis, determining the timing characteristics, etc. are dependent to a great extent on the electrical properties of the wiring. Interconnect analysis plays a critical role in the design of chips with small feature sizes that are designed to operate at high speeds. An aspect of the present invention is the provision of a method and apparatus for extracting capacitances to model and employ the results obtained for the interconnect wiring for VLSI chips. Because interconnect wiring on a VLSI chip generally encompass millions of miniature shapes, a very efficient approach needs to be employed. Besides being fast, the method must determine capacitances accurately enough for subsequent analysis to have any value. In this document, we first describe the capacitance ascertainment technique and then provide the processes involved in the implementation.
The following explanation will help in understanding the complexity of the problem solved by the present invention, and in understanding terms used in describing the invention. Common circuit connection points are herein referred to as ports of VLSI devices. Ports are typically connected by means of wires running in the various wiring planes of the VLSI chip. Wires in different metal layers are connected by means of vias. A net is a set of wires tied together electrically and used to connect a set of ports. The spaces between two wires consist of a dielectric material and/or air. Many dielectrics are usable, however the dielectric is usually silicon dioxide. To analyze the electrical properties of the interconnect wiring, it is necessary to determine the capacitance between each wire of one net that has capacitive coupling to a wire belonging to different net. Each such pair of coupled wires is herein referred to as being a wire pair. The pair of nets to which the coupled wires belong is herein referred to as a net pair. A coupling capacitance is defined for each net pair (n.sub.i, n.sub.j) as the sum of a plurality of coupling capacitances of the wire pairs (w.sub.i, w.sub.j), where w.sub.i belongs to n.sub.i and w.sub.j belongs to n.sub.j. In a practical application a coupling capacitance between two wires is determined only if the wires are in each others proximity. When nets are not in proximity to each other their coupling capacitances are negligibly small. Another capacitance of a wire that is important, called the self capacitance, is that due to the wire's interaction with a reference point that is usually ground.
Wiring levels in a VLSI chip are located above the substrate in a fixed number of metal wiring layers determined by the technology used to fabricate the VLSI chip. In each wiring level, wires are laid either front to back and/or from left to right, when the chip is being viewed from the front with the substrate located at the bottom. The plane of the chip's cross-section that can be seen when the chip is viewed from the front or the back of the chip is herein called the frontal plane (XZ plane). The plane of the cross-section of the chip as seen when viewing the chip from the left or the right is herein called the lateral plane (YZ-plane). A plane of the cross-section that is seen when viewing the chip from the top or bottom is called the wiring plane (XY-plane). The frontal direction (X) is the direction that is orthogonal to the frontal plane and the lateral direction (Y) is the direction orthogonal to the lateral plane. The via direction (Z) is orthogonal to the wiring plane. The X, Y and Z symbols shown in parenthesis provide a short hand notation for these definitions.
FIG. 1 shows an example geometry 100 of a set of crossing wires and the capacitances that are typically required to be determined for such a geometry. Wires labeled w.sub.2 102, and w.sub.3 103, are located in metal layers above and below the metal layer on which the wire labeled w.sub.1 101, is located, respectively. Furthermore, wires w.sub.2 102, and w.sub.3 103, are parallel to each other and are both orthogonal to the wire w.sub.1 101. FIG. 2 shows the capacitances that need to be determined and the equivalent circuit for this configuration of wires. In this circuit, capacitances c.sub.12 112, c.sub.23 123, and c.sub.13 113 are the coupling capacitances between wires w.sub.1 101 and w.sub.2 102, w.sub.2 102 and w.sub.3 103, and, w.sub.1 101 and w.sub.3 103, respectively. Capacitances c.sub.11 111, c.sub.22 122, and c.sub.33 133 are the self capacitances of wires w.sub.1 101, w.sub.2 102, and w.sub.3 104, respectively.
The typical wiring configuration used to interconnect devices on a VLSI chip has many layers and many wires in each layer of metal. As a result, this requires the processing of a very large number of capacitances. In determining these capacitances, it is customary to use a geometry engine to decompose the wiring geometry into manageable units. The capacitance values for each of these units are determined independently. Finally, the determined values are combined to obtain the required capacitance values for the entire geometry. For the purpose of describing the present invention, it is assumed that such a geometry engine is available. Furthermore, it is assumed that each wire is decomposed into rectangular pieces called conductor segments. A conductor segment belongs to the net that contains the wire to which the conductor segment belongs. An environment of a particular conductor segment contains all other conductor segments that are in that particular conductor segment's vicinity, and the spatial separations between them. Environment information includes the sizes and distances of neighboring conductor segments in all the three X, Y and Z dimensions. The geometry engine that decomposes wires into conductor segments, and determines its environment, is based on the well known scan line processor or any other processor that decomposes the geometry efficiently.
An example of a conductor segment and its environment is shown in FIG. 3. In this example there are three metal layers. The particular conductor segment in consideration is labeled con.sub.c 302. This conductor segment is part of wire-w 301 located in metal layer m.sub.2 311. The portions of wire-w 301 that are not part of con.sub.c are not cross-hatched. There are four conductor segments in the environment of con.sub.c 302. Two of them are located in metal layer m.sub.2 311. They are con.sub.l 306 and con.sub.r 303 located to the left and right of con.sub.c 302, respectively. Conductor segment con.sub.b 304 is located on metal layer m.sub.1 312 below con.sub.c 302, and conductor segment con.sub.t 305 is located in metal layer m.sub.3 313 above m.sub.2 311. Coordinate axes X 307, Y 308, and Z 309 are shown in the figure. The frontal plane, lateral plane, and wiring planes are the XZ, YZ and XY planes, respectively. In general the environment of a particular conductor segment could be more complex. A conductor segment generally has many other conductor segments in front, behind or diagonally above or beneath itself.
Given the unit of decomposed geometry, the capacitance processing method described in this document efficiently determines various capacitance values for a multitude of such units. This approach for determining capacitances is also referred to herein as the subcapacitance method or the subcapacitance approach.
Since the number of units of decomposed geometries is extremely large, typically in the order of tens of millions of units even for the simplest of VLSI chips, the capacitance processing must be performed very fast to have any practical use. This requires that the number of arithmetic operations for the capacitance determinations be minimized to save determination time. However, the number of combinations of conductor arrangements that can occur is so large that methods of fitting approximate capacitance formulae are too inaccurate and hence inadequate. Other accurate methods that rely upon solutions to field equations are too slow to cope with the size of the problem.